In conventional processing systems, the output device is typically a display for providing a visual representation, in addition to utilizing mass storage for storage of data, etc. When utilizing a display as compared to mass storage, it is desirable to apportion a predetermined amount of the processing time of an associated processor to the task of updating the display. In any type of processing system, this display updating operation can be the "weak link" in the overall operation of the system. This is typically due to the interconnecting scheme between the processing unit and the display or displays.
In one multiple display system, as disclosed in U.S. Pat. No. 4,800,376, issued Jan. 24, 1989 to Suga, et al., a multiple display system is provided that utilizes a plurality of display elements with decoders associated with each of the display elements. However, this system, although utilizing multiple displays or display elements, still utilizes a single data input for providing data to the system, with the data then routed to the various display elements. Therefore, the limiting factor to display updating is the speed of the data that can be input to the overall display system. Since all display data is input through a single data input, the display bandwidth is governed by this data input. The addition of displays requires a higher bandwidth input to maintain the same display update rates.
Another system, that described in U.S. Pat. No. 4,845,480, issued Jul. 4, 1989 to Satou, discloses a system utilizing a frame memory for storing original data with a plurality of display memories for storing image data. Each of the display memories is associated with a display unit for displaying the image represented by the data stored in each of the associated display memories. Image data transferred from the display memory is performed through a programmable data conversion memory such that the data conversion is performed independent of data manipulation of the frame memory. However, even with this type of system, the updating of the display memories is achieved through a single path. Since there is only a single processing center for interfacing with the original data.
Another disadvantage to systems of the prior art is that they are not "scalable". That is, the display size is fixed by the computer manufacturer relative to the processing power. Even though systems, such as that described in the Suga, et al. patent, have provided for expanded display systems, they have still required the same processing power to service and update all of the displays. There is a significant limitation in bandwidth between the processor portion of the system and the display portion since typically only a single data input is provided for the expanded displays.